1. Field of the Invention
The present invention relates to a semiconductor memory device, in particular, to a semiconductor memory device using ferroelectric materials as its memory cells.
2. Description of the Related Art
As can be seen from FIG. 12, ferroelectric materials take two charge (polarization) quantity (Q) states (basic points A, D) when application voltage Vf is zero. This is because the spontaneous polarization has a hysteresis characteristic. These two states correspond to a binary condition. In this way, a semiconductor memory device using ferroelectric materials as its memory cells (hereinafter, referred to as a ferroelectric memory) can store binary data when the power supply is switched off. Each memory cell comprises a ferroelectric capacitor having a structure in which a ferroelectric film is interposed between two electrodes. One electrode is connected to a bit line; the other, to a plate line for generating a voltage between bit lines.
When data is read, for example, a voltage −VINT is applied to the ferroelectric film. As a result, the states of the ferroelectric film individually transfer to operating points B and C at which the hysteresis curve intersects straight line L1 or L2. The straight line L1 or L2 corresponds to the capacitance of the bit line (capacitor connected to bit line and the sum of parasitic capacitance). Thus, voltages corresponding to the operating points B and C are applied to the bit line. The following reference potential is prepared independently. More specifically, the reference potential is the intermediate between potentials VH and VL at operating points B and C using the potential −VINT as the basis. The reference potential and the potentials VH and VL are compared and amplified. The reference potential can be generated by properly setting an operating point P using a ferroelectric capacitor. In this case, a ferroelectric capacitor having a hysteresis characteristic such that the operating point P is properly positioned is used.
In the foregoing description, the voltage −VINT is used; therefore, the operating points B and C transfer in a negative region of the Y-axis (negative operating region). The ferroelectric capacitor for memory and reference voltage generation operates in the same operating region. However, depending on the configuration of the ferroelectric memory, positive and negative voltages are both used by several ferroelectric capacitors. When a voltage +VINT is used, operating points E and F transfer in a positive region of the Y-axis (positive operating region), and a potential set the potential +VINT as the basis is used. In such a ferroelectric memory, potential absolute value obtained from the potential +VINT or −VINT is used, and thereby, data can be read according to the same method regardless of positive and negative operating regions.
FIG. 13 shows a typical example of memory cells using both positive and negative voltages when reading data from a ferroelectric capacitor. FIG. 14 is a circuit diagram showing parts shown in FIG. 13 and its peripheral parts. FIG. 15 is a timing chart to explain the operation of FIG. 14.
As shown in FIG. 14 and FIG. 15, transistors T0 to T7 are powered on in the standby mode. In other words, no voltage is applied to memory capacitors C0 to C7. For example, when data is read from the memory capacitor C0, bit lines BL are /BL are in a floating state. The transistor T0 is powered off while a cell block select transistor ST0 is powered on. In this state, a plate line PL is set to a drive potential VINT, and thereby, the data of the capacitor C0 is read to the bit line BL. Simultaneously, a block select transistor BST is powered on, and a dummy plate line DPL is set to a drive potential VINT. By doing so, a reference potential is read from a reference potential capacitor RC to the bit line /BL.
When data is read from the memory capacitor C0, only transistor T0 is powered off. Thus, as seen from FIG. 13, the top electrode of the memory capacitor C0 is connected to the bit line BL while the bottom electrode thereof is connected to the plate line PL via transistors T1 to T6. Therefore, voltage is applied from the bottom electrode of the memory capacitor C0 toward the top electrode thereof. The same operation as above is carried out in memory capacitors C2, C4 and C6.
On the other hand, when data is read from the memory capacitor C1, only transistor T1 is powered off. Therefore, the bottom electrode of the memory capacitor C1 is connected to the bit line BL via the transistor T0 while the top electrode thereof is connected to the plate line PL via transistors T2 to T7. Thus, voltage is applied from the bottom electrode of the capacitor C1 toward the top electrode thereof, that is, in the direction opposite to that is the case of the memory capacitor C0. The same operation as above is carried out in memory capacitors C3, C5 and C7.
Incidentally, the same directional voltage is always applied to the reference potential capacitor RC. In other words, the reference potential capacitor RC always operates in either the positive or negative region. Even if the memory capacitors C0 to C7 take positive and negative operating regions, the reference potential is set to be positioned at the approximately intermediate potential between read potentials VH and VL in either the positive or negative region. The absolute value of the reference potential is used in the positive and negative operating regions. The hysteresis characteristic of the ferroelectric capacitor is symmetrical with respect to the Y-axis. Therefore, memory cell capacitors C0 to C7 operate in the same manner regardless of the operating region.
The hysteresis characteristic of FIG. 12 may be distorted as shown in FIG. 16 depending on conditions when forming the ferroelectric capacitor (initial imprint). As a result, the hysteresis characteristic becomes non-symmetrical with respect to the Y-axis. Incidentally, memory capacitors C0 to C7 and reference potential capacitor RC all have nearly the same hysteresis characteristic because of having substantially the same configuration. If the hysteresis characteristic becomes non-symmetrical, the absolute value of the potential at the operating point is different depending on whether the capacitor is operated and in which region it is operated.
As described above, the memory capacitors C0 to C7 take both positive and negative operating regions. However, the operating point of the reference potential capacitor RC is set to a proper position in one of the positive and negative region (e.g., negative region). Thus, if the memory capacitors C0 to C7 operate in the other region (e.g., positive region), the operating point of the reference potential capacitor RC is largely shifted from the intermediate point between operating points E and F of the memory capacitors C0 to C7. As a result, the data read margin is reduced.